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LTC3209-1/LTC3209-2 600mA Main/Camera LED Controller DESCRIPTIO
The LTC (R)3209-1/LTC3209-2 are highly integrated multidisplay LED controllers. These parts contain a high efficiency, low noise charge pump to provide power to MAIN, CAM and AUX LED displays. The LTC3209-1/ LTC3209-2 require only four small ceramic capacitors and one current set resistor to form a complete LED power supply and current controller. The maximum display currents are set by a single external resistor. Current for each LED is controlled by a precision internal current source. Dimming and On/Off for all displays is achieved via the I2C serial interface. 256 states are available for the MAIN display. Sixteen states are available for the CAM display and four states are available for the AUX display. The charge pump optimizes efficiency based on the voltage across the LED current sources. The part powers up in 1x mode and will automatically switch to boost mode whenever any enabled MAIN or CAM LED current source begins to enter dropout. The first dropout switches the part into 1.5x mode and a subsequent dropout switches the part into 2x mode. The part resets to 1x mode whenever a data bit is updated via the I2C port. The parts are available in a 4mm x 4mm 20-lead QFN package.
FEATURES

Multimode Charge Pump Provides Up to 94% Efficiency (1x, 1.5x, 2x) Up to 600mA Total Output Current LTC3209-1: 8 Current Sources Available as 6 x 25mA MAIN, 1 x 400mA CAM and 1 x 15mA AUX LTC3209-2: 8 Current Sources Available as 5 x 25mA MAIN, 2 x 200mA CAM and 1 x 15mA AUX LED On/Off and Brightness Level Programmable Using 2-Wire I2CTM Interface Automatic Charge Pump Mode Switching or Fixed Mode for Power Supply Generation Low Noise Constant Frequency Operation* Internal Soft-Start Limits Inrush Current During Start-up and Mode Switching Short Circuit/Thermal/Open-Shorted LED Protection 256 Brightness States for MAIN Display 16 Brightness States for CAM Display 4 Brightness States for AUX Display 20-Lead (4mm x 4mm) QFN Package
APPLICATIO S
Video/Camera Phones with QVGA+ Displays
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. *Protected by U.S. Patents, including 6411531
TYPICAL APPLICATIO
2.2F 2.2F
LTC3209-1 6 MAIN/1 CAM Operation
2.2F
LTC3209-2 5 MAIN/2 CAM Operation
2.2F
C1P C1M C2P C2M VBAT 2.2F LTC3209-1 SCL I2C VBAT1,2 CPO
2.2F
MAIN
CAM VBAT RED 2.2F
C1P C1M C2P C2M VBAT1,2 LTC3209-2 SCL CPO
6 SDA MAIN1-6 CAM
I2C
SDA
MAIN1-5 CAM 2
LOW HI
CAMHL RREF 24.3k
AUX GND
3209 TA01
LOW HI
CAMHL RREF 24.3k
AUX GND
U
5
U
U
2.2F
MAIN
CAM RED
3209 TA02
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1
LTC3209-1/LTC3209-2
ABSOLUTE
(Note 1)
AXI U RATI GS
ICAM1-2 (Note 5) .................................................. 250mA ICAM (Note 5) ...................................................... 500mA CPO, RREF Short-Circuit Duration ....................Indefinite Operating Temperature Range (Note 2) .. -40C to 85C Storage Temperature Range ................. -65C to 125C
VBAT, DVCC, CPO to GND ............................... -0.3 to 6V SDA, SCL, CAMHL ..................... -0.3V to (DVCC + 0.3V) ICPO (Note 4)....................................................... 700mA IMAIN1-6 (Note 5) ................................................... 31mA IAUX (Note 5) ......................................................... 30mA
PACKAGE/ORDER I FOR ATIO
TOP VIEW
VBAT1 C1M C2M C1P C2P
VBAT1
C1M RREF
20 19 18 17 16 CPO 1 MAIN1 2 MAIN2 3 MAIN3 4 MAIN4 5 6
MAIN5
20 19 18 17 16 15 SCL 14 SDA CPO 1 MAIN1 2 MAIN2 3 MAIN3 4 MAIN4 5 6 7 8 9 10 21 15 SCL 14 SDA 13 CAMHL 12 CAM2 11 CAM1
21
13 CAMHL 12 CAM 11 DVCC
7
MAIN6
8
AUX
9 10
VBAT2 RREF
MAIN5
AUX
UF PACKAGE 20-LEAD (4mm x 4mm) PLASTIC QFN
UF PACKAGE 20-LEAD (4mm 4mm) PLASTIC QFN
TJMAX = 125C, JA = 40C/W EXPOSED PAD IS GND (PIN 21), MUST BE SOLDERED TO PCB
TJMAX = 125C, JA = 40C/W EXPOSED PAD IS GND (PIN 21), MUST BE SOLDERED TO PCB
ORDER PART NUMBER LTC3209EUF-1
UF PART MARKING 32091
ORDER PART NUMBER LTC3209EUF-2
VBAT2
DVCC
C2M
C1P
C2P
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBAT1,2 = 3.6V, DVCC = 3V, RREF = 24.3k, C1 = C2 = C3 = C4 = 2.2F, unless otherwise noted.
PARAMETER VBAT Operating Voltage IVBAT Operating Current ICPO = 0, 1x Mode, LED Disabled ICPO = 0, 1.5x Mode ICPO = 0, 2x Mode
ELECTRICAL CHARACTERISTICS
CONDITIONS
VBAT UVLO Threshold DVCC Operating Voltage DVCC Operating Current DVCC UVLO Threshold VBAT Shutdown Current DVCC = 3V
DVCC = 1.8V, Serial Port Idle
2
U
U
W
WW U
W
TOP VIEW
UF PART MARKING 32092
MIN 2.9
TYP 0.4 2.7 4.5 1.5
MAX 4.5
UNITS V mA mA mA V
1.5 1 3
4.5 1 7
V A V A
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LTC3209-1/LTC3209-2
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBAT1,2 = 3.6V, DVCC = 3V, RREF = 24.3k, C1 = C2 = C3 = C4 = 2.2F, unless otherwise noted.
PARAMETER White LED Current (MAIN1-6), 8-Bit Linear DAC Full-Scale LED Current Minimum (1LSB) LED Current LED Current Matching LED Dropout Voltage Full-Scale LED Current Minimum (1LSB) LED Current CONDITIONS MAIN = 1V MAIN = 1V Any Two MAIN Outputs at 50% FS Mode Switch Threshold, IMAINx = FS CAM = 1V CAM = 1V

ELECTRICAL CHARACTERISTICS
MIN 25
TYP 28 110 1 180
MAX 31
UNITS mA A % mV
White LED Current (CAM), LTC3209-1, 4-Bit Linear DAC 360 400 26.8 400
440
mA mA mV
LED Dropout Voltage Mode Switch Threshold, ICAM = FS White LED Current (CAM1-2), LTC3209-2, 4-Bit Linear DAC Full-Scale LED Current Minimum (1LSB) LED Current LED Current Matching LED Dropout Voltage AUX LED Current, 2-Bit Linear DAC Full-Scale LED Current Minimum (1LSB) LED Current VOL Charge Pump (CPO) 1x Mode Output Impedance 1.5x Mode Output Impedance 2x Mode Output Impedance CPO Voltage Regulation CLOCK Frequency SDA, SCL, CAMHL VIL (Low Level Input Voltage) VIH (High Level Input Voltage) VOL, Digital Output Low (SDA) IIH IIL Serial Port Timing (Notes 6, 7) tSCL tBUF tHD,STA tSU,STA tSU,STO tHD,DAT(OUT) tHD,DAT(IN) tSU,DAT tLOW tHIGH tf tr Clock Operating Frequency Bus Free Time Between Stop and Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time Input Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock Data Fall Time Clock Data Rise Time 1.3 0.6 0.6 0.6 0 0 100 1.3 0.6 20 20 IPULLUP = 3mA SDA, SCL, CAMHL = DVCC SDA, SCL, CAMHL = 0V

CAM = 1V CAM = 1V CAM1-2 at 50% FS Mode Switch Threshold, ICAM = FS AUX = 1V AUX = 1V IAUX = 1mA; C0, C1 = High
180
200 13.3 1 400
220
mA mA % mV
12.5
13.75 4.4 18 0.5 2.7 3.2 4.6 5.1 0.85
15
mA mA mV V V MHz
VBAT = 3V, VCPO = 4.2V (Note 3) VBAT = 3V, VCPO = 4.8V (Note 3) 1.5x Mode, ICPO = 2mA 2x Mode, ICPO = 2mA
0.3 * DVCC 0.7 * DVCC 0.16 -1 -1 0.4 1 1 400
V V V A A kHz s s s s ns ns ns s s ns ns
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900
300 300
3
LTC3209-1/LTC3209-2
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. VBAT1,2 = 3.6V, DVCC = 3V, RREF = 24.3k, C1 = C2 = C3 = C4 = 2.2F, unless otherwise noted.
PARAMETER tSP RREF VRREF RRREF CONDITIONS Spike Suppression Time RREF = 24.3k Reference Resistor Range
ELECTRICAL CHARACTERISTICS
MIN 50 1.20 20
TYP
MAX
UNITS ns V k
1.23
1.26 30
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LTC3209-1/LTC3209-2 are guaranteed to meet performance specifications from 0C to 70C. Specifications over the -40C to 85C ambient operating temperature range are assured by design, characterization and correlation with statistical process controls.
Note 3: 1.5x mode output impedance is defined as (1.5VBAT - VCPO)/IOUT. 2x mode output impedance is defined as (2VBAT - VCPO)/IOUT. Note 4: Based on long term current density limitations. Assumes an operating duty cycle of 10% under absolute maximum conditions for duration less than 10 seconds. Max Charge Pump current for continuous operation is 300mA. Note 5: Based on long term current density limitations. Note 6: All values are referrenced to VIH and VIL levels. Note 7: Guaranteed by design.
TYPICAL PERFOR A CE CHARACTERISTICS TA = 25C unless otherwise noted
Mode Switch Fast Dropout Times
2x 1.5x 1x VCPO 1V/DIV
VBAT = 3.6V REGC C2 = Hi 1ms/DIV
320912 G01
1x Mode Switch Resistance vs Temperature
0.65 0.60
SWITCH RESISTANCE ()
ICPO = 200mA
OPEN-LOOP OUTPUT RESISTANCE ()
0.55 0.50 0.45 0.40 0.35 -40
VBAT = 3.6V VBAT = 3.3V VBAT = 3.9V
2.8 2.6 2.4 2.2 2.0 -40
CPO VOLTAGE (V)
-15
10 35 TEMPERATURE (C)
4
UW
60 85
3209 G05
1.5x Mode CPO Ripple
2x Mode CPO Ripple
VCPO 20mV/DIV AC COUPLED VBAT = 3.6V ICPO = 200mA CCPO = 2.2F 500ns/DIV
320912 G02
VCPO 20mV/DIV AC COUPLED VBAT = 3.6V ICPO = 200mA CCPO = 2.2F 500ns/DIV
320912 G03
1.5x Mode Charge Pump OpenLoop Output Resistance vs Temperature (1.5VBAT-VCPO)/ICPO
3.2 3.0 VBAT = 3V VCPO = 4.2V C2 = C3 = C4 = 2.2F
4.8 4.6 4.4 4.2
1.5x Mode CPO Voltage vs Load Current
C2 = C3 = C4 = 2.2F
3.6V
VBAT = 3V 3.1V 4.0 3.2V 3.3V 3.4V 3.8 3.5V 3.6 0 100 200 300 400 LOAD CURRENT (mA) 500
3209 G07
-15
10 35 TEMPERATURE (C)
60
85
3209 G06
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LTC3209-1/LTC3209-2 TYPICAL PERFOR A CE CHARACTERISTICS TA = 25C unless otherwise noted
2x Mode Charge Pump Open-Loop Output Resistance vs Temperature (2VBAT-VCPO)/ICPO
3.8
OPEN-LOOP OUTPUT RESISTANCE ()
3.6 3.4 3.2 3.0 2.8
DVCC SHUTDOWN CURRENT (A)
VBAT = 3V VCPO = 4.8V C2 = C3 = C4 = 2.2F CPO VOLTAGE (V)
2.6 -40
-15
10 35 TEMPERATURE (C)
VBAT Shutdown Current vs VBAT Voltage
5.5 DVCC = 3V
400 380
VBAT SHUTDOWN CURRENT (A)
5.0 4.5 TA = 85C 4.0 3.5 TA = 25C 3.0 TA = -40C 2.5 2.0 1.5 2.7 3 3.9 3.6 3.3 VBAT VOLTAGE (V) 4.2 4.5
3209 G12
VBAT CURRENT (A)
340 320 300 280 260 240 220 200 2.7 3.0 3.6 3.9 3.3 VBAT VOLTAGE (V) 4.2 4.5
3209 G13
SUPPLY CURRENT (mA)
2x Mode Supply Current vs ICPO (IVBAT-2ICPO)
25 VBAT = 3.6V
400
CAM PIN CURRENT (mA)
CAM PIN CURRENT (mA)
20
SUPPLY CURRENT (mA)
15
10
5
0
0
100
300 400 200 LOAD CURRENT (mA)
UW
60 85
3209 G08
2x Mode CPO Voltage vs Load Current
5.2 5.1 5.0 4.9 4.8 4.7 4.6 4.5 4.4 4.3 4.2 0 100 300 400 200 LOAD CURRENT (mA) 500
3209 G09
DVCC Shutdown Current vs DVCC Voltage
0.7 VBAT = 3.6V TA = -40C 0.5 TA = 85C 0.4 0.3 0.2 0.1 0 2.7 TA = 25C
C2 = C3 = C4 = 2.2F 3.4V 3.5V
0.6
3.3V 3.2V 3.1V VBAT = 3V
3
3.9 3.6 3.3 DVCC VOLTAGE (V)
4.2
4.5
3209 G11
1x Mode No Load VBAT Current vs VBAT Voltage
30
1.5x Mode Supply Current vs ICPO (IVBAT-1.5ICPO)
VBAT = 3.6V
360
20
10
0 0 100 200 300 400 LOAD CURRENT (mA) 500
3209 G14
LTC3209-1 CAM Pin Current vs CAM Pin Voltage
VBAT = 3.6V 400 360 320 280 240 200 160 120 80 40
LTC3209-1 CAM Pin Current vs Input Code
VBAT = 3.6V
300
200
100
500
3209 G15
0
0 0 0.2 0.6 0.8 0.4 CAM PIN VOLTAGE (V) 1.0
3209 G22
0123456789ABCDEF HEX CODE
3209 G23
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5
LTC3209-1/LTC3209-2 TYPICAL PERFOR A CE CHARACTERISTICS TA = 25C unless otherwise noted
LTC3209-1 CAM Pin Dropout Voltage vs CAM Pin Current
400
CAM PIN DROPOUT VOLTAGE (mV)
360 320
VBAT = 3.6V
CAM PIN CURRENT (mA)
280 220 200 160 120 80 40 0 0 200 100 300 CAM PIN CURRENT (mA) 400
3209 G24
CAM PIN CURRENT (mA)
LTC3209-2 CAM Pin Dropout Voltage vs CAM Pin Current
400
CAM PIN DROPOUT VOLTAGE (mV)
360 320 280 220 200 160 120 80 40 0
VBAT = 3.6V
MAIN PIN CURRENT (mA)
20 15 10 5 0 0 0.2 VBAT = 3.6V 0.4 0.6 0.8 MAIN PIN VOLTAGE (V) 1.0
3209 G26
0
100 50 150 CAM PIN CURRENT (mA)
200
3209 G24
MAIN PIN CURRENT (mA)
MAIN Pin Dropout Voltage vs MAIN Pin Current
200 VBAT = 3.6V 16 14 AUX PIN CURRENT (mA) 12 10 8 6 4 2 0 0 5 15 20 25 10 MAIN PIN CURRENT (mA) 30
3209 G27
MAIN PIN DROPOUT VOLTAGE (V)
180 160 140 120 100 80 60 40 20 0
EFFICIENCY (PLED/PIN) (%)
6
UW
LTC3209-2 CAM Pin Current vs CAM Pin Voltage
200 VBAT = 3.6V 200 180 160 160 140 120 100 80 60 40 20 0 0 0.2 0.6 0.8 0.4 CAM PIN VOLTAGE (V) 1.0
3209 G16
LTC3209-2 CAM Pin Current vs Input Code
VBAT = 3.6V
120
80
40
0
0123456789ABCDEF HEX CODE
3209 G17
MAIN Pin Current vs MAIN Pin Voltage
30 25
MAIN Pin Current vs Input Code
28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 VBAT = 3.6V
0 10 20 30 40 50 60 70 80 90 A0 B0 C0D0 E0 F0 FF HEX CODE
3209 G17
AUX Pin Current vs Input Code
VBAT = 3.6V VAUX = 1V
100 90 80 70 60 50 40 30 20 10
6-LED MAIN Display Efficiency vs VBAT
6 LEDS AT 15mA/LED (TYP VF AT 15mA = 3.2V) 3.0 3.2 3.4 3.6 3.8 VBAT (V) 4.0 4.2 4.4
0
1 HEX CODE
2
3
3209 G20
0
3209 G21
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LTC3209-1/LTC3209-2
PI FU CTIO S (LTC3209-1/LTC3209-2)
CPO (Pin 1/Pin 1): Output of the Charge Pump Used to Power LEDs. A 2.2F X5R or X7R ceramic capacitor should be connected to ground. MAIN1-6 (Pins 2, 3, 4, 5, 6, 7, LTC3209-1): Current Source Outputs for the MAIN Display White LEDs. The LEDs on the MAIN display can be set from 0mA to 28mA in 256 steps via software control and internal 8-bit linear DAC. Each output can be disabled externally by connecting the output to CPO. Setting data in REGA to 0 disables all MAIN outputs. MAIN1-5 (Pins 2, 3, 4, 5, 6, LTC3209-2): Current Source Outputs for the MAIN Display White LEDs. The LEDs on the MAIN display can be set from 0mA to 28mA in 256 steps via software control and internal 8-bit linear DAC. Each output can be disabled externally by connecting the output to CPO. Setting data in REGA to 0 disables all MAIN outputs. AUX (Pin 8/Pin 7): Current Source Output for the AUX Display LED. The LED current source can be set from 0mA to 13.75mA in 4 steps via software control and internal 2bit DAC. AUX does not have dropout sensing and cannot be disabled by connecting to CPO. This pin can also be used as an I2C controlled general purpose output. VBAT2,1 (Pins 9, 18/Pins 8, 18): Supply Voltage for the Entire Device. Two separate pins are used to isolate the charge pump from the analog sections to reduce noise. Both pins must be connected together externally and bypassed with a single 2.2F low ESR ceramic capacitor close to VBAT1. VBAT2 may require a 0.1F capacitor. RREF (Pin 10/Pin 9): This pin controls the maximum amount of LED current for all displays. The RREF voltage is 1.23V. An external 24.3k resistor to ground sets the reference currents for all display DACs and support circuits for nominal MAIN full-scale current of 28mA and total CAM full-scale current of 400mA. The value for RREF is limited to a range of 20k to 30k. DVCC (Pin 11/Pin 10): Supply Voltage for All Digital I/O Lines. This pin sets the logic reference level of the LTC3209-1/LTC3209-2. Decouple DVCC to GND with a 0.1F capacitor. A UVLO circuit on the DVCC pin forces all registers to all 0s whenever DVCC is below the UVLO threshold. CAM1-2 (Pins 11, 12, LTC3209-2): Current Source Outputs for the CAM1 and CAM2 Display White LEDs. The LEDs on the two CAM displays can each be set from 0mA to 200mA in 16 steps via software control and internal 4-bit linear DAC. Two 4-bit registers are available. One is used to program the high camera current and the second the low camera current. These registers can be selected via the serial port or the CAMHL pin. Each output can be disabled by connecting the output to CPO. Setting data in REGB to 0 disables both CAM outputs. (See Applications Information). CAM (Pin 12, LTC3209-1): Current Source Output for the CAM Display White LED. The LED on the CAM display can be set from 0mA to 400mA in 16 steps via software control and internal 4-bit linear DAC. Two 4-bit registers are available. One is used to program the high camera current and the second the low camera current. These registers can be selected via the serial port or the CAMHL pin. Each output can be disabled by connecting the output to CPO. Setting data in REGB to 0 disables the CAM output. (See Applications Information). CAMHL (Pin 13/Pin 13): This pin selects CAM high current register when asserted high and CAM low current register when low. The high to low transition automatically resets the charge pump mode to 1x. SDA (Pin 14/Pin 14): I2C Data Input for the Serial Port. Serial data is shifted in one bit per clock to control the LTC3209-1/LTC3209-2. The logic level is referenced to DVCC. SCL (Pin 15/Pin 15): I2C Clock Input. The logic level for SCL is referenced to DVCC. C1P, C2P, C1M, C2M (Pins 20, 19, 17, 16/Pins 20, 19, 17, 16): Charge Pump Flying Capacitor Pins. A 2.2F X7R or X5R ceramic capacitor should be connected from C1P to C1M and C2P to C2M. Exposed Pad (Pin 21/Pin 21): System Ground. Connect Exposed Pad to PCB ground plane.
U
U
U
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LTC3209-1/LTC3209-2
BLOCK DIAGRA
850kHz OSCILLATOR
VBAT1
-
VBAT2
+
MAIN1
+ -
RREF DVCC CAMHL 1.23V CAM CURRENT SOURCES CONTROL LOGIC 2 MAIN CURRENT SOURCES 6
SDA
SCL
320912 BD
8
W
C1P C1M C2P C2M GND CPO CHARGE PUMP ENABLE CP MAIN2 MAIN3 MAIN4 MAIN5 MAIN6 (LTC3209-1) CAM1 CAM2 (LTC3209-2) AUX CURRENT SOURCE AUX MASTER/SLAVE REG SHIFT REGISTER
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LTC3209-1/LTC3209-2 OPERATIO
The LTC3209-1 has 6 MAIN outputs, 1 CAM output and 1 AUX output. The LTC3209-2 has 5 MAIN outputs, 2 CAM outputs and 1 AUX output. Power Management The LTC3209-1/LTC3209-2 use a switched capacitor charge pump to boost CPO to as much as 2 times the input voltage up to 5.1V. The part starts up in 1x mode. In this mode, VBAT is connected directly to CPO. This mode provides maximum efficiency and minimum noise. The LTC3209-1/LTC3209-2 will remain in 1x mode until a MAIN or CAM LED current source drops out. Dropout occurs when a current source voltage becomes too low for the programmed current to be supplied. When dropout is detected, the LTC3209-1/LTC3209-2 will switch into 1.5x mode. The CPO voltage will then start to increase and will attempt to reach 1.5x VBAT up to 4.6V. Any subsequent dropout will cause the part to enter the 2x mode. The CPO voltage will attempt to reach 2x VBAT up to 5.1V. The part will be reset to 1x mode whenever a DAC data bit is updated via the I2C port or on the falling edge of the CAMHL signal. A 2-phase nonoverlapping clock activates the charge pump switches. In the 2x mode the flying capacitors are charged on alternate clock phases from VBAT to minimize input current ripple and CPO voltage ripple. In 1.5x mode the flying capacitors are charged in series during the first clock phase and stacked in parallel on VBAT during the second phase. This sequence of charging and discharging the flying capacitors continues at a constant frequency of 850kHz. The currents delivered by the LED current sources are controlled by an associated DAC. Each DAC is programmed via the I2C port.
U
Soft-Start Initially, when the part is in shutdown, a weak switch connects VBAT1 to CPO. This allows VBAT1 to slowly charge the CPO output capacitor and prevent large charging currents to occur. The LTC3209-1/LTC3209-2 also employs a soft-start feature on its charge pump to prevent excessive inrush current and supply droop when switching into the step-up modes. The current available to the CPO pin is increased linearly over a typical period of 125s. Soft-start occurs at the start of both 1.5x and 2x mode changes. Charge Pump Strength When the LTC3209-1/LTC3209-2 operate in either 1.5x mode or 2x mode, the charge pump can be modeled as a Thevenin-equivalent circuit to determine the amount of current available from the effective input voltage and effective open-loop output resistance, ROL (Figure 1). ROL is dependent on a number of factors including the switching term, 1/(2fOSC * CFLY), internal switch resistances and the nonoverlap period of the switching circuit. However, for a given ROL, the amount of current available will be directly proportional to the advantage voltage of 1.5VBAT - CPO for 1.5x mode and 2VBAT - CPO for 2x mode.
ROL
+
CPO
+ -
1.5VBAT OR 2VBAT
-
320912 F01
Figure 1. Charge Pump Thevenin Equivalent Open-Loop Circuit
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LTC3209-1/LTC3209-2 OPERATIO
Consider the example of driving white LEDs from a 3.1V supply. If the LED forward voltage is 3.8V and the current sources require 100mV, the advantage voltage for 1.5x mode is 3.1V * 1.5 - 3.8V - 0.1V or 750mV. Notice that if the input voltage is raised to 3.2V, the advantage voltage jumps to 900mV--a 20% improvement in available strength. From Figure 1, for 1.5x mode the available current is given by:
IOUT = 1.5VBAT - VCPO ROL
For 2x mode, the available current is given by:
IOUT =
2VBAT - VCPO ROL
3.2
OPEN-LOOP OUTPUT RESISTANCE ()
3.0 2.8 2.6 2.4 2.2
OPEN-LOOP OUTPUT RESISTANCE ()
VBAT = 3V VCPO = 4.2V C2 = C3 = C4 = 2.2F
2.0 -40
Figure 2. Typical 1.5x ROL vs Temperature
10
U
Notice that the advantage voltage in this case is 3.1V * 2 - 3.8V - 0.1V = 2.3V. ROL is higher in 2x mode but a significant overall increase in available current is achieved. Typical values of ROL as a function of temperature are shown in Figures 2 and 3. Shutdown Current Shutdown occurs when all the current source data bits have been written to zero or when DVCC is below the DVCC UVLO threshold. Although the LTC3209-1/LTC3209-2 is designed to have very low shutdown current, it will draw about 3A from VBAT when in shutdown. Internal logic ensures that the LTC3209-1/LTC3209-2 is in shutdown when DVCC is grounded. Note, however that all of the logic signals that are referenced to DVCC (SCL, SDA, CAMHL) will need to be at DVCC or below (i.e., ground) to avoid violation of the absolute maximum specifications on these pins.
3.8 3.6 3.4 3.2 3.0 2.8 2.6 -40 VBAT = 3V VCPO = 4.8V C2 = C3 = C4 = 2.2F -15 10 35 TEMPERATURE (C) 60 85
3209 G06
-15
10 35 TEMPERATURE (C)
60
85
3209 G08
Figure 3. Typical 2x ROL vs Temperature
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LTC3209-1/LTC3209-2 OPERATIO
Serial Port The microcontroller compatible I2C serial port provides all of the command and control inputs for the LTC3209-1/ LTC3209-2. Data on the SDA input is loaded on the rising edge of SCL. D7 is loaded first and D0 last. There are three data registers and one address register. Once all address bits have been clocked into the address register acknowledge occurs. After the data registers have been written a load pulse is created after the stop bit. The load pulse transfers all of the data held in the data registers to the DAC registers. At this point the LED current will be changed to the new settings. The serial port uses static logic registers so there is no minimum speed at which it can be operated. MAIN Current Sources LTC3209-1 There are six MAIN current sources. These current sources have an 8-bit linear DAC for current control. For RREF = 24.3k, the output current range is 0mA to 28mA in 256 steps. The current sources are disabled when a block receives an all zero data word. The supply current for that block is reduced to zero. In addition unused LED outputs can be connected to CPO to turn off the current source output and reduce the operating current to typically 10A. LTC3209-2 There are five MAIN current sources. These current sources have an 8-bit linear DAC for current control. For RREF = 24.3k, the output current range is 0mA to 28mA in 256 steps. The current sources are disabled when a block receives an all zero data word. The supply current for that block is reduced to zero. In addition unused LED outputs can be connected to CPO to turn off the current source output and reduce the operating current to typically 10A.
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Camera Current Sources LTC3209-1 There is one CAM current source. This current source has a 4-bit linear DAC for current control. The output current range is 0mA to 400mA in 16 steps (RREF = 24.3k). The current source is disabled when the block receives an all zero data word. The supply current for the block is reduced to zero. In addition, the LED output can be connected to CPO to turn off the current source output and reduce operating current to typically 10A. This pin cannot be allowed to float if unused since dropout will be erroneously detected. LTC3209-2 There are two CAM current sources. These current sources have a 4-bit linear DAC for current control. The output current range of each current source is 0mA to 200mA in 16 steps (RREF = 24.3k). The current sources are disabled when the block receives an all zero data word. The supply current for the block is reduced to zero. In addition unused LED outputs can be connected to CPO to turn off the current source output and reduce the operating current to typically 10A. These pins cannot be allowed to float if unused since dropout will be erroneously detected. Auxiliary Current Source There is one AUX current source. This current source has a 2-bit Linear DAC for current control. The output current range is 0mA to 13.75mA in 4 steps (OFF, 33%, 67%, 100%). The AUX output does not have dropout detection and cannot be disabled when connected to CPO. The current source is disabled when the block receives an all zero data word and the supply current for the block is reduced to zero. This output can also be used as an I2C controlled digital open-drain general purpose output.
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LTC3209-1/LTC3209-2 OPERATIO
CAMHL The CAMHL pin quickly selects the camera high register for flash applications without reaccessing the I2C port. When low the CAM current range will be controlled by the camera low 4-bit register. When CAMHL is asserted high the current range will be set by the camera high 4-bit register. The dropout delay is reduced from 150ms to 2ms when CAMHL is asserted high so that the charge pump can quickly change modes if required. When CAMHL is asserted from high to low the charge pump mode is reset to 1x. Thermal Protection The LTC3209-1/LTC3209-2 have built-in overtemperature protection. At internal die temperatures of around 150C thermal shutdown will occur. This will disable all of the current sources and charge pump until the die has cooled by about 15C. This thermal cycling will continue until the fault has been corrected. RREF Current Set Resistor The current set resistor is connected between the RREF pin and ground. This resistor sets the full-scale current for all three displays (MAIN, CAM and AUX) according to the following equations:
MAIN = CAM = CAM = AUX = 1.23V * 550 RREF (LTC3209-1) 0 (LTC3209-2)
1.23V * 7900 RREF 1.23V * 3950 RREF 1.23V * 272 RREF
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A 24.3k, 1% resistor provides full-scale currents of 28mA for the MAIN; 400mA (total) current for CAM and 13.75mA for AUX current sources. This input is protected against shorts to ground or low value resistors <10k. When a fault is detected the reference current amplifier is current limited. In addition the current source outputs and charge pump are disabled. Mode Switching The LTC3209-1/LTC3209-2 will automatically switch from 1x mode to 1.5x mode and subsequently to 2x mode whenever a dropout condition is detected at an LED pin. Dropout occurs when a current source voltage becomes too low for the programmed current to be supplied. When switching modes the mode change will not occur unless dropout has existed for 150ms. This delay will allow the LEDs to warm up and achieve the final LED forward voltage value. The dropout delay can be reduced to 2ms by programming the Drop2ms bit C2 in the REGC register or when the CAMHL pin is switched high when controlling the CAM LEDs. The mode will automatically switch back to 1x whenever a data bit is updated via the I2C port or when CAMHL switches from high to low. If the part is forced into either 1.5x mode or 2x mode to operate as a fixed voltage power supply over I2C, no mode switching will occur until an I2C update is given.
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OPERATIO
FORCE 2X
FORCE IP5 DTH2 DTH1
SCAMHILO DROP2MS DAUX1 DAUX0
MAIN CAM HI CAM LO B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 REGC STOP 1 0 ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK B7 B6 B5 B4 B3 B2 B1 7 8 9 1 2 3 4 5 6 7 8 6 5 4 3 2 1 B0 ACK C7 C6 C5 C4 C3 C2 C1 C0 ACK REGB A2 A1 A0 B7 B6 B5 WR 1 0 REGA A7 A6 A5 A4 A3
0
0
1
1
0
1
ADDRESS BYTE
START
SDA
0
0
1
1
0
1
SCL
1 7 8 9 1 2 3 4 5 6 7 8 9
2
3
4
5
6
9
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Figure 4. Bit Assignments
SDA tSU, DAT tLOW tHD, DAT tSU, STA tHD, STA tBUF tSU, STO
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SCL tHIGH tr tf REPEATED START CONDITION tSP STOP CONDITION
tHD, STA START CONDITION
START CONDITION
Figure 5. Timing Parameters
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ADDRESS
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LTC3209-1/LTC3209-2 OPERATIO
MSB A7 MAIN D7 A6 MAIN D6 A5 MAIN D5 A4 MAIN D4 A3 MAIN D3 A2 MAIN D2 A1 MAIN D1 REGA, MAIN LED 8-Bit DAC Data LSB A0 MAIN D0
REGB, CAMERA LED 4-Bit High and 4-Bit Low DAC Data MSB B7 CAM D3 B6 CAM D2 HIGH BITS B5 CAM D1 LSB B4 CAM D0 MSB B3 CAM D3 B2 CAM D2 LOW BITS B1 CAM D1 LSB B0 CAM D0
REGC, AUX Data and Option Byte MSB C7 Force2x DAUX0 DAUX1 Drop2ms Scamhilo Dth1 Dth2 Force1p5 Force2x 1 0 1 0 0 0 1 0 1 0 C6 Force1p5 C5 Dth2 C4 Dth1 C3 Scamhilo C2 Drop2ms C1 DAUX1 LSB C0 DAUX0
AUX DAC Data (LSB) AUX DAC Data (MSB) Changes Dropout Time from 150ms to 2ms Dropout Time is 150ms Unless CAMHL is Enabled and High Selects CAM High Register, Disables CAMHL Pin Selects CAM Low Register, Enables CAMHL Pin Must Always be 0 (Test Mode) Must Always be 0 (Test Mode) Forces Charge Pump into 1.5x Mode, CPO Regulates at 4.6V Enables Mode Logic to Control Mode Changes Based on Dropout Signal Forces Charge Pump into 2x Mode, Overrides Force1p5 Signal, CPO Regulates at 5.1V Enables Mode Logic to Control Mode Changes Based on Dropout Signal
I2C Interface The LTC3209-1/LTC3209-2 communicates with a host (master) using the standard I2C 2-wire interface. The Timing Diagram (Figure 5) shows the timing relationship of the signals on the bus. The two bus lines, SDA and SCL, must be high when the bus is not in use. External pull-up resistors or current sources, such as the LTC1694 SMBus accelerator, are required on these lines. The LTC3209-1/LTC3209-2 is a receive-only (slave) device.
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Bus Speed The I2C port is designed to be operated at speeds of up to 400kHz. It has built-in timing delays to ensure correct operation when addressed from an I2C compliant master device. It also contains input filters designed to suppress glitches should the bus become corrupted.
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LTC3209-1/LTC3209-2 OPERATIO
START and STOP Conditions A bus-master signals the beginning of a communication to a slave device by transmitting a START condition. A START condition is generated by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the slave, it issues a STOP condition by transitioning SDA from low to high while SCL is high. The bus is then free for communication with another I2C device. Byte Format Each byte sent to the LTC3209-1/LTC3209-2 must be 8 bits long followed by an extra clock cycle for the Acknowledge bit to be returned by the LTC3209-1/LTC32092. The data should be sent to the LTC3209-1/LTC3209-2 most significant bit (MSB) first. Acknowledge The Acknowledge signal is used for handshaking between the master and the slave. An Acknowledge (active low) generated by the slave (LTC3209-1/LTC3209-2) lets the master know that the latest byte of information was received. The Acknowledge related clock pulse is generated by the master. The master releases the SDA line (high) during the Acknowledge clock cycle. The slave-receiver must pull down the SDA line during the Acknowledge clock pulse so that it remains a stable low during the high period of this clock pulse. Slave Address The LTC3209-1/LTC3209-2 responds to only one 7-bit address which has been factory programmed to 0011011. The eighth bit of the address byte (R/W) must be 0 for the LTC3209-1/LTC3209-2 to recognize the address since it is a write only device. This effectively forces the address to be 8 bits long where the least significant bit of the address is 0. If the correct seven bit address is given but the R/W bit is 1, the LTC3209-1/LTC3209-2 will not respond.
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Bus Write Operation The master initiates communication with the LTC3209-1/ LTC3209-2 with a START condition and a 7-bit address followed by the Write Bit R/W = 0. If the address matches that of the LTC3209-1/LTC3209-2, the part returns an Acknowledge. The master should then deliver the most significant data byte. Again the LTC3209-1/LTC3209-2 acknowledges and cycle is repeated two more times for a total of one address byte and three data bytes. Each data byte is transferred to an internal holding latch upon the return of an Acknowledge. After all three data bytes have been transferred to the LTC3209-1/LTC3209-2, the master may terminate the communication with a STOP condition. Alternatively, a REPEAT-START condition can be initiated by the master and another chip on the I2C bus can be addressed. This cycle can continue indefinitely and the LTC3209-1/LTC3209-2 will remember the last input of valid data that it received. Once all chips on the bus have been addressed and sent valid data, a global STOP condition can be sent and the LTC3209-1/LTC3209-2 will update all registers with the data that it had received. In certain circumstances the data on the I2C bus may become corrupted. In these cases the LTC3209-1/ LTC3209-2 responds appropriately by preserving only the last set of complete data that it has received. For example, assume the LTC3209-1/LTC3209-2 has been successfully addressed and is receiving data when a STOP condition mistakenly occurs. The LTC3209-1/LTC3209-2 will ignore this STOP condition and will not respond until a new START condition, correct address, new set of data and STOP condition are transmitted. Likewise, if the LTC3209-1/LTC3209-2 was previously addressed and sent valid data but not updated with a STOP, it will respond to any STOP that appears on the bus with only one exception, independent of the number of REPEAT-STARTs that have occurred. If a REPEAT-START is given and the LTC3209-1/LTC3209-2 successfully acknowledges its address, it will not respond to a STOP until all bytes of the new data have been received and acknowledged.
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LTC3209-1/LTC3209-2
APPLICATIO S I FOR ATIO
VBAT, CPO Capacitor Selection The style and value of the capacitors used with the LTC3209-1/LTC3209-2 determine several important parameters such as regulator control loop stability, output ripple, charge pump strength and minimum start-up time. To reduce noise and ripple, it is recommended that low equivalent series resistance (ESR) ceramic capacitors are used for both CVBAT and CCPO. Tantalum and aluminum capacitors are not recommended due to high ESR. The value of CCPO directly controls the amount of output ripple for a given load current. Increasing the size of CCPO will reduce output ripple at the expense of higher start-up current. The peak-to-peak output ripple of the 1.5x mode is approximately given by the expression:
VRIPPLE(P-P) =
IOUT 3fOSC * CCPO
Where fOSC is the LTC3209-1/LTC3209-2 oscillator frequency or typically 850kHz and CCPO is the output storage capacitor. The output ripple in 2x mode is very small due to the fact that load current is supplied on both cycles of the clock. Both style and value of the output capacitor can significantly affect the stability of the LTC3209-1/LTC3209-2. As shown in the Block Diagram, the LTC3209-1/LTC3209-2 use a control loop to adjust the strength of the charge pump to match the required output current. The error signal of the loop is stored directly on the output capacitor. The output capacitor also serves as the dominant pole for the control loop. To prevent ringing or instability, it is important for the output capacitor to maintain at least 1F of capacitance over all conditions. In addition, excessive output capacitor ESR will tend to degrade the loop stability. If the output capacitor has 160m or more of ESR, the closed-loop frequency response will cease to roll off in a simple one-pole fashion and poor load transient response or instability may occur. Multilayer ceramic chip capacitors typically have exceptional ESR performance. MLCCs combined with a tight board layout will result in very good stability. As the
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value of CCPO controls the amount of output ripple, the value of CVBAT controls the amount of ripple present at the input pin (VBAT). The LTC3209-1/LTC3209-2 input current will be relatively constant while the charge pump is either in the input charging phase or the output charging phase but will drop to zero during the clock nonoverlap times. Since the nonoverlap time is small (~25ns), these missing "notches" will result in only a small perturbation on the input power supply line. Note that a higher ESR capacitor such as tantalum will have higher input noise due to the higher ESR. Therefore, ceramic capacitors are recommended for low ESR. Input noise can be further reduced by powering the LTC32091/LTC3209-2 through a very small series inductor as shown in Figure 6. A 10nH inductor will reject the fast current notches, thereby presenting a nearly constant current load to the input power supply. For economy, the 10nH inductor can be fabricated on the PC board with about 1cm (0.4") of PC board trace.
VBAT LTC3209-1 LTC3209-2 GND
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Figure 6. 10nH Inductor Used for Input Noise Reduction (Approximately 1cm of Board Trace)
Flying Capacitor Selection Warning: Polarized capacitors such as tantalum or aluminum should never be used for the flying capacitors since their voltage can reverse upon start-up of the LTC3209-1/LTC3209-2. Ceramic capacitors should always be used for the flying capacitors. The flying capacitors control the strength of the charge pump. In order to achieve the rated output current it is necessary to have at least 1.6F of capacitance for each of the flying capacitors. Capacitors of different materials lose their capacitance with higher temperature and voltage at different rates. For example, a ceramic capacitor made of X7R material will retain most of its capacitance from -40C to 85C whereas a Z5U or Y5V style capacitor will
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LTC3209-1/LTC3209-2
APPLICATIO S I FOR ATIO
lose considerable capacitance over that range. Z5U and Y5V capacitors may also have a very poor voltage coefficient causing them to lose 60% or more of their capacitance when the rated voltage is applied. Therefore, when comparing different capacitors, it is often more appropriate to compare the amount of achievable capacitance for a given case size rather than comparing the specified capacitance value. For example, over rated voltage and temperature conditions, a 1F, 10V, Y5V ceramic capacitor in a 0603 case may not provide any more capacitance than a 0.22F, 10V, X7R available in the same case. The capacitor manufacturer's data sheet should be consulted to determine what value of capacitor is needed to ensure minimum capacitances at all temperatures and voltages. Table 1 shows a list of ceramic capacitor manufacturers and how to contact them:
Table 1. Recommended Capacitor Vendors
AVX Kemet Murata Taiyo Yuden Vishay www.avxcorp.com www.kemet.com www.murata.com www.t-yuden.com www.vishay.com
CPO VBAT1 C4 GND GND DVCC RREF VBAT PLANE LAYER VBAT C6 GND GND VBAT2 R1 C5 C3 C1 GND SOLDER SIDE COMPONENT GND PLANE LAYER C2 VBAT ALL VIAS LABELED GND ARE CONNECTED TO GND PLANE LAYER ALL VIAS LABELED VBAT ARE CONNECTED TO VBAT PLANE LAYER
Layout Considerations and Noise Due to the high switching frequency and the transient currents produced by the LTC3209-1/LTC3209-2, careful board layout is necessary. A true ground plane and short connections to all capacitors will improve performance and ensure proper regulation under all conditions. The flying capacitor pins C1P, C2P, C1M and C2M will have high edge rate waveforms. The large dv/dt on these pins can couple energy capacitively to adjacent PCB runs. Magnetic fields can also be generated if the flying capacitors are not close to the LTC3209-1/LTC3209-2 (i.e., the loop area is large). To decouple capacitive energy transfer, a Faraday shield may be used. This is a grounded PCB trace between the sensitive node and the LTC3209-1/ LTC3209-2 pins. For a high quality AC ground, it should be returned to a solid ground plane that extends all the way to the LTC3209-1/LTC3209-2.
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The following guidelines should be followed when designing a PCB layout for the LTC3209. * The Exposed Pad should be soldered to a large copper plane that is connected to a solid, low impedance ground plane using plated, through-hole vias for proper heat sinking and noise protection. * Input and output capacitors (C1 and C4) must be placed close to the part. * The flying capacitors (C2 and C3) must be placed close to the part. The traces running from the pins to the capacitor pads should be as wide as possible. * VBAT, CPO traces must be made wide to minimize inductance and handle the high currents. * LED pads must be large and connected to other layers of metal to ensure proper heat sinking.
GND
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Figure 7. PC Board Layout Example (LTC3209-1)
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LTC3209-1/LTC3209-2
APPLICATIO S I FOR ATIO
Power Efficiency To calculate the power efficiency () of a white LED driver chip, the LED power should be compared to the input power. The difference between these two numbers represents lost power whether it is in the charge pump or the current sources. Stated mathematically, the power efficiency is given by:
=
PLED PIN
The efficiency of the LTC3209-1/LTC3209-2 depends upon the mode in which it is operating. Recall that the LTC3209-1/LTC3209-2 operates as a pass switch, connecting VBAT to CPO, until dropout is detected at the ILED pin. This feature provides the optimum efficiency available for a given input voltage and LED forward voltage. When it is operating as a switch, the efficiency is approximated by:
= PLED = PIN VBAT
( (
VLED
* ILED *
) = VLED IBAT ) VBAT
(1x Mode)
since the input current will be very close to the sum of the LED currents. At moderate to high output power, the quiescent current of the LTC3209-1/LTC3209-2 is negligible and the expression above is valid. Once dropout is detected at the LED pin, the LTC3209-1/ LTC3209-2 enables the charge pump in 1.5x mode.
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In 1.5x boost mode, the efficiency is similar to that of a linear regulator with an effective input voltage of 1.5 times the actual input voltage. This is because the input current for a 1.5x charge pump is approximately 1.5 times the load current. In an ideal 1.5x charge pump, the power efficiency would be given by:
IDEAL = VLED * ILED VLED PLED = = PIN VBAT * (1.5) * ILED 1.5 * VBAT
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(
(
)
)(
)
(1.5x Mode) Similarly, in 2x boost mode, the efficiency is similar to that of a linear regulator with an effective input voltage of 2 times the actual input voltage. In an ideal 2x charge pump, the power efficiency would be given by: IDEAL = VLED * ILED VLED PLED = = PIN 2 * VBAT VBAT * (2) * ILED
(
(
)
)(
)
(2x Mode) Thermal Management For higher input voltages and maximum output current, there can be substantial power dissipation in the LTC3209-1/LTC3209-2. If the junction temperature increases above approximately 150C the thermal shutdown circuitry will automatically deactivate the output current sources and charge pump. To reduce maximum junction temperature, a good thermal connection to the PC board is recommended. Connecting the Exposed Pad to a ground plane and maintaining a solid ground plane under the device will reduce the thermal resistance of the package and PC board considerably.
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LTC3209-1/LTC3209-2
PACKAGE DESCRIPTIO
4.50 0.05 3.10 0.05 2.45 0.05 (4 SIDES)
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 2.45 0.10 (4-SIDES) 0.75 0.05 R = 0.115 TYP 19 20 0.38 0.10 1 2 PIN 1 NOTCH R = 0.30 TYP
NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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UF Package 20-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1710)
0.70 0.05 PACKAGE OUTLINE 0.25 0.05 0.50 BSC
(UF20) QFN 10-04
0.200 REF 0.00 - 0.05
0.25 0.05 0.50 BSC
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LTC3209-1/LTC3209-2
TYPICAL APPLICATIO
4 LED MAIN, 1 LED SUB, 400mA CAM LED Controller Plus Regulated Output
C2 2.2F C3 2.2F 4x25mA MAIN
C1P C1M C2P C2M VBAT C1 2.2F DVCC C6 0.1F C5 0.1F CPO VBAT1 VBAT2 LTC3209-1 MAIN1 DVCC MAIN2 MAIN3 MAIN4 MAIN5 SCL MAIN6 SDA AUX CAMHL RREF R1 24.3k CAM GND
I2C TORCH FLASH
RELATED PARTS
PART NUMBER LTC3200-5 LTC3201 LTC3202 LTC3205 LTC3206 LTC3208 LTC3214 LTC3215 LTC3216 LTC3217 LTC3251 LTC3440 DESCRIPTION Low Noise, 2MHz Regulated Charge Pump White LED Driver Low Noise, 1.7MHz Regulated Charge Pump White LED Driver Low Noise, 1.5MHz Regulated Charge Pump White LED Driver Multidisplay LED Controller I2C Multidisplay LED Controller High Current Software Configurable Multidisplay LED Controller 500mA Camera LED Charge Pump 700mA Low Noise High Current LED Charge Pump 1A Low Noise High Current White LED Driver 600mA Low Noise Multi-LED Camera Light 500mA (IOUT), 1MHz to 1.6MHz Spread Spectrum Step-Down Charge Pump 600mA (IOUT), 2MHz Synchronous Buck-Boost DC/DC Converter COMMENTS Up to 6 White LEDs, VIN: 2.7V to 4.5V, VOUT(MAX) = 5V, IQ = 8mA, ISD 1A, ThinSOT Package Up to 6 White LEDs, VIN: 2.7V to 4.5V, VOUT(MAX) = 5V, IQ = 6.5mA, ISD 1A, 10-Lead MS Package Up to 8 White LEDs, VIN: 2.7V to 4.5V, VOUT(MAX) = 5V, IQ = 5mA, ISD 1A, 10-Lead MS Package 92% Efficiency, VIN: 2.8V to 4.5V, IQ = 50A, ISD 1A, (4mm x 4mm) QFN Package 92% Efficiency, 400mA Continuous Output Current. Up to 11 White LEDs in (4mm x 4mm) QFN Package 95% Efficiency, VIN: 2.9V to 4.5V, VOUT(MAX): 5.5V, IQ = 280A, ISD < 1A, (5mm x 5mm) QFN-32 Package 94% Efficiency, VIN: 2.9V to 4.5V, IQ = 300A, ISD < 2.5A, 500mA Output Current, 10-Lead (3mm x 3mm) DFN Package VIN: 2.9V to 4.4V, VOUT(MAX) = 5.5V, IQ = 300A, ISD < 2.5A (3mm x 3mm) DFN Package 93% Efficiency, 1A Output Current, 12-Lead (3mm x 4mm) DFN Package, Independent Low/High Current Programming VIN: 2.9V to 4.4V, IQ = 400A, Four Outputs, (3mm x 3mm) 16-Lead DFN Package 85% Efficiency, VIN: 3.1V to 5.5V, VOUT: 0.9V to 1.6V, IQ = 9A, ISD 1A, 10-Lead MS Package 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.5V, IQ = 25A, ISD 1A, 10-Lead MS Package
ThinSOT is a trademark of Linear Technology Corporation.
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 FAX: (408) 434-0507
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C4 2.2F 1x15mA 1x400mA AUX CAM 5.1V, 2x MODE 4.6V, 1.5x MODE SPEAKER EN
3209 TA03
320912fa LT 0506 REV A * PRINTED IN USA
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2005

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